Method and apparatus for transmitting data

ABSTRACT

A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.

FIELD OF THE INVENTION

[0001] The present invention generally relates to methods oftransferring data between a data-transmitter and a data-receiver. Morespecifically, the invention relates to data-transmitters,data-receivers, and methods of broadcasting data onto a bus that reduceeffective capacitive coupling (and data errors resulting from suchcapacitive coupling) between parallel interconnects during such datatransfers.

BACKGROUND

[0002] In modern microprocessors, large numbers of interconnect wires,i.e., electrical conductors, connect various circuits. Many of theseelectrical conductors, such as metal traces in integrated circuits, runparallel for significant distances, and are therefore subject to noisefrom capacitive coupling. Such parallel metal traces may be on a singlemetallization layer within an integrated circuit. Alternatively, suchparallel metal traces may be on different metallization layers within anintegrated circuit. Capacitive coupling between parallel electricalconductors can create significant time delays. In addition, as discussedin U.S. Pat. No. 6,189,133 to Durham et al., capacitive coupling ofparallel electrical conductors may result in false signal transitions indynamic and self-timed circuits if the electrical conductors exceed 300to 500 μm in length.

[0003] Thus, it could be desirable to provide a method and apparatus foravoiding capacitive coupling of parallel electrical conductors.

SUMMARY OF INVENTION

[0004] One embodiment of the invention is a data-transmitter fortransmitting data. The data-transmitter includes a data-driving circuit.The data-driving circuit can output a first plurality of data values viaa first plurality of data-output ports and can output a second pluralityof data values via a second plurality of data-output ports. Thedata-transmitter also includes a plurality of data-delay circuits. Eachof the inputs of the plurality of data-delay circuits is coupled to oneof the second plurality of data-output ports. The data-transmitter alsoincludes a plurality of electrical conductors. Each of the plurality ofelectrical conductors is coupled to one of the first plurality ofdata-output ports.

[0005] Another embodiment of the invention is a data-transmitter fortransmitting data. The data-transmitter includes a data-driving circuit.The data-driving circuit can output a first plurality of data values viaa first plurality of data-output ports and can output a second pluralityof data values via a second plurality of data-output ports. Thedata-transmitter also includes a clock-delay circuit. The input of theclock-delay circuit is coupled to the first plurality of data-outputports and can strobe the first plurality of data-output ports. Theoutput of the clock-delay circuit is coupled to the second plurality ofdata-output ports and can strobe the second plurality of data-outputports.

[0006] Still another embodiment of the invention is a data-receiver forreceiving data. The data-receiver includes a plurality of data-delaycircuits. The data-receiver also includes a plurality of electricalconductors and a data-receiving circuit. The data-receiving circuitincludes a first plurality of data-input ports and a second plurality ofdata-input ports. The first plurality of data-input ports can receive,sample, and store a first plurality of data values. The second pluralityof data-input ports can receive, sample, and store a second plurality ofdata values. Each of the outputs of the plurality of data-delay circuitsis coupled to one of the first plurality of data-input ports of thedata-receiving circuit. Each of the plurality of electrical conductorsis coupled to one of the second plurality of data-input ports of thedata-receiving circuit.

[0007] Yet another embodiment of the invention is another data-receiverfor receiving data. This data-receiver includes a clock-delay circuit.The clock-delay circuit can delay a clock signal and can output adelayed-clock signal. The data-receiver also includes a first pluralityof data-ports. The first plurality of data-ports can receive a firstportion of data. The first plurality of data-ports is coupled to thesecond plurality of data-ports and can be strobed by the clock signal.The data-receiver also includes a second plurality of data-ports. Thesecond plurality of data-ports can receive a second portion of data. Thesecond plurality of data-ports can be strobed by the delayed-clocksignal.

[0008] Still another embodiment is a method of broadcasting N, an eveninteger, bits of data onto a bus that includes a first plurality ofelectrical conductors and a second plurality of electrical conductors.The method includes: broadcasting a first portion of data that includesN/2 bits of data onto the first plurality of electrical conductors.Then, after a time period has elapsed that is greater than 0 seconds andless than the time period required to transfer 2 bits of datasequentially on one of the first plurality of electrical conductors,broadcasting a second portion of data that includes N/2 bits of dataonto the second plurality of electrical conductors.

BRIEF DESCRIPTION OF THE FIGURES

[0009]FIG. 1 presents one embodiment of a data-transmitter

[0010]FIG. 2 presents another embodiment of a data-transmitter

[0011]FIG. 3 presents one embodiment of a data-receiver.

[0012]FIG. 4 presents another embodiment of a data-receiver.

[0013]FIG. 5 presents a system for transferring data from adata-transmitter to a data-receiver.

[0014]FIG. 6 presents a flow chart of a method of broadcasting data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The following description is presented to enable any personskilled in the art to make and use the invention, and is provided in thecontext of a particular application and its requirements. Variousmodifications to the disclosed embodiments will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to other embodiments and applications without departing fromthe spirit and scope of the present invention. Thus, the presentinvention is not intended to be limited to the embodiments shown, but isto be accorded the widest scope consistent with the principles andfeatures disclosed herein.

5.1 Embodiments of Data-Transmitters

[0016] One embodiment of the invention, which is shown in FIG. 1, is adata-transmitter 100. The data-transmitter 100 can broadcast a portionof data, such as the odd data-bits of a byte of data, onto a bus andthen broadcast another portion of data, such as the even data-bits of abyte of data, onto the bus at a time that is slightly after the timethat the first portion of data was broadcast. As a result, effectivecapacitive coupling between adjacent bits in the bus is reduced.

[0017] As shown in FIG. 1, the data-transmitter 100 includes adata-driving circuit 105. The data-driving circuit 105 can output afirst plurality of data values via a first plurality of data-outputports 110. In addition, the data-driving circuit 105 can output a secondplurality of data values via a second plurality of data-output ports115. For example, in some embodiments of the invention, the data-drivingcircuit 105 could output even-numbered data-bits of a data-byte via thefirst plurality of data-output ports 110 and could output odd-numbereddata-bits of the data-byte via the second plurality of data-output ports115. In other embodiments of the invention, the data-driving circuit 105could output odd-numbered data-bits via the first plurality ofdata-output ports 110 and could output even-numbered data-bits via thesecond plurality of data-output ports 115.

[0018] While FIG. 1 shows a data-transmitter 100 that includes 8data-output ports, other data-transmitters could have any number ofdata-output ports, such as 2, 4, 16, 32, 64, or 128 data-output ports.Thus, if the data-transmitter is a register within a microprocessor, theregister could broadcast a portion of a byte, a byte, or multiple bytesof data to a microprocessor bus via a number of data-output ports.

[0019] Referring again to FIG. 1, the data-transmitter 100 also includesa plurality of data-delay circuits 120. The inputs of the data-delaycircuits are coupled to the second plurality of data-output ports 115.In some embodiments of the invention, such as in embodiments utilized inmicroprocessors, the data-delay circuits could include two invertersplaced in series. These two inverters could delay data by 75 ps or more.Such a delay is approximately equal to ¾ of the transition time (100 ps)of data-bits in modern microprocessors.

[0020] The data-transmitter 100 also includes a plurality of electricalconductors 125. As shown in FIG. 1, the electrical conductors 125 arecoupled to the first plurality of data-output ports 110. As is evidentfrom FIG. 1, in some embodiments of the invention, a electricalconductor 125 a, 125 b, or 125 c is positioned between adjacentdata-delay circuits 120 a-120 b, 120 b-120 c, or 120 c-120 d.

[0021] In some embodiments of the invention, the data-transmitter 100could also include a clock-driving circuit 130. The clock-drivingcircuit could be operable to output a clock signal via a clock-outputport 135. In some embodiments, such as is shown in FIG. 1, thedata-transmitter 100 could also include a clock-delay circuit 140. Insuch embodiments, the clock-delay circuit 140 could delay the clock bythe same amount that the data-delay circuits 120 delay data.

[0022] During operation, the data-transmitter 100 would typically becoupled to a bus (not shown), which may include a plurality ofrelatively long parallel electrical conductors, such as metal traces.When the data-transmitter 100 begins its sequence of steps to broadcastdata onto the bus, the data driving circuit 105 would first output datavia the first and second pluralities of data-output ports 110 and 115.In some embodiments of the invention, such as shown in FIG. 1, the datawould be output to the first and second plurality of data-output ports110 and 115 at approximately the same time. A first portion of the datawould be immediately broadcast to the bus. On the other hand, thedata-delay circuits 120 would delay the broadcast of the second portionof the data for a short period of time. Thus, if the delay of the secondportion of the data is sufficient, then each electrical conductor in thebus that is undergoing a signal transition would be adjacent to one ormore “quiet” electrical conductors in which no signal transition isoccurring. As a result, the effective capacitive coupling betweenadjacent bits in the bus would be reduced.

5.2 Other Embodiments of Data-Transmitters

[0023] Another embodiment of the invention is a data-transmitter 200,which is shown in FIG. 2. This data-transmitter is also able tobroadcast a portion of data onto a bus and then broadcast anotherportion of data onto the bus at a time that is slightly after the timethat the first portion of data was broadcast.

[0024] As shown in FIG. 2, the data-transmitter 200 includes adata-driving circuit 205. The data-driving circuit 205 can output afirst plurality of data values via a first plurality of data-outputports 210. In addition, the data-driving circuit 205 can output a secondplurality of data values via a second plurality of data-output ports215.

[0025] While the data-transmitter 200 shown in FIG. 2 contains 8data-output ports, in other embodiments of the invention, the number ofdata-output ports can vary. For example, the number of data-output portscould be 2, 4, 16, 32, 64, 128 or more. Thus, in some embodiments of theinvention, the first plurality of data-output ports 210 would beoperable to output a first portion of a byte of data and the secondplurality of data-output ports 215 would be operable to output a secondportion of the byte of data.

[0026] Referring again to FIG. 2, a clock signal 245 is coupled to andoperable to strobe the first plurality of data-output ports 210. Theclock signal 245 is also input into a clock-delay circuit 240. Theclock-delay circuit 240 can be similar to the clock-delay circuit 140discussed above. The output of the clock-delay circuit 240 is coupled toand operable to strobe the second plurality of data-output ports 215. Asa result, the first plurality of data-output ports 210 can broadcastdata slightly before the second plurality of data-output ports 215broadcasts data. If the difference between the time that the first andsecond portions of data are broadcast is equal to or greater than ¾ ofthe transition time of the data-bits on a bus (not shown), then theeffective capacitive coupling between adjacent data-bits on the bus canbe significantly reduced.

[0027] In some embodiments of the invention, such as shown in FIG. 2,the data-transmitter 200 may also include a clock driving circuit 230that is operable to output a clock via a clock-output port 235. In stillother embodiments (not shown), the data-transmitter 200 may also drive adelayed clock signal onto a bus (not shown).

5.3 Embodiments of Data-Receivers

[0028] Another embodiment of the invention, which is shown in FIG. 3, isa data-receiver 300. The data-receiver 300 can receive a portion of datafrom a bus and then can receive another portion of data from the bus ata time that is slightly after the time that the first portion of datawas received. Because the data-receiver 300 can receive portions of dataat different times, the data can be accurately received, sampled andstored after the data has been broadcast onto the bus by adata-transmitter such as discussed above and then transferred by the busin a manner that reduces effective capacitive coupling between adjacentbits in the bus.

[0029] As shown in FIG. 3, the data-receiver 300 includes a plurality ofdata-delay circuits 325. In addition, the data-receiver 300 includes aplurality of electrical conductors 320. The data-receiver 300 alsoincludes a data-receiving circuit 305.

[0030] The data-receiving circuit 305 includes a first plurality ofdata-input ports 310 and a second plurality of data-input ports 315. Thefirst plurality of data-input ports 310 can receive, sample, and store afirst plurality of data values. Similarly, the second plurality ofdata-input ports 315 can receive, sample, and store a second pluralityof data values. For example, the first plurality of data-input ports310, as shown in FIG. 3, could receive, sample, and store the odd bitsof a byte of data while the second plurality of data-input ports 315could receive, sample, and store the even bits of the byte of data. Inother embodiments of the invention, the first plurality of data-inputports 310 could receive, sample, and store the even bits of the byte ofdata and the second plurality of data-input ports 315 could receive,sample, and store the odd bits of the byte of data.

[0031] Referring again to FIG. 3, the outputs of each of the pluralityof data-delay circuits are coupled to one of the first plurality ofdata-inputs 310. Similarly, each of the plurality of electricalconductors 320 is coupled to one of the second plurality of data-inputports 315.

[0032] During operation, the data-receiver 300 could be coupled to a bus(not shown), which may include a plurality of relatively long parallelelectrical conductors. When the data-receiver 300 begins its sequence ofsteps to receive data from the bus, the data-delay circuits 325 wouldreceive a first portion of data. After a predetermined delay, thedata-delay circuits 325 would output the first portion of data to thefirst plurality of data-input ports 310 at approximately the same timethat the second plurality of data-input ports 315 would be receiving thesecond portion of data from the bus. As a result, the first plurality ofdata-input ports 310 would receive the first portion of the data atapproximately the same time that the second plurality of data-inputports 315 would receive the second portion of the data. After thedata-input ports 315 and 310 receive the data, the data-input portswould sample and store the data.

[0033] In some embodiments of the invention, the data-receiver 300 alsoincludes a clock-delay circuit 340. As shown in FIG. 3, the output ofthe clock-delay circuit 340 could be coupled to a clock-receivingcircuit 330. Usage of a clock-delay circuit 340 in the data-receiver 300could be useful to synchronize a clock signal, which has not beendelayed by a data-transmitter, with data that has been delayed by adata-transmitter.

5.4 Other Embodiments of Data-Receivers

[0034] Another embodiment of the invention, which is shown in FIG. 4, isanother data-receiver 400 that can receive a first portion of data froma bus and then receive a second portion of data from the bus at a timethat is slightly after the time that the first portion of data wasreceived. Because the data-receiver 400 can receive portions of data atdifferent times, the data can be transferred on the bus in a manner thatreduces effective capacitive coupling between adjacent bits in the bus.

[0035] As shown in FIG. 4, the data-receiver 400 includes a clock-delaycircuit 440. The clock-delay circuit 440 can delay a clock signal andcan output a delayed-clock signal.

[0036] Referring again to FIG. 4, the data-receiver 400 includes a firstplurality of data ports 410. The first plurality of data-ports 410 canreceive a first portion of data. The first plurality of data-ports 410is coupled to the input of the clock-delay circuit 440. Thus, the firstplurality of data-ports 410 can be strobed by the clock signal.

[0037] The data-receiver 400 also includes a second plurality of dataports 415. The second plurality of data-ports 415 can receive a secondportion of data. The second plurality of data-ports 415 is coupled tothe output of the clock-delay circuit 440. Thus, the second plurality ofdata-ports 415 can be strobed by the delayed-clock signal.

[0038] In some embodiments of the invention, the data-receiver may alsoinclude a clock-receiving circuit 430. The clock receiving circuit 430could be coupled to the clock-delay circuit 440.

[0039] During operation, the data-receiver 400 would typically becoupled to a bus (not shown). When the data-receiver 400 begins itssequence of steps to receive data from the bus, the first plurality ofdata-input ports 410 would be strobed by the clock signal. When thefirst plurality of data-input ports 410 is strobed by the clock signal,the first plurality of data-input ports 410 would receive, sample, andstore the first portion of data.

[0040] Slightly after the time that the first plurality of data-inputports 410 is strobed by the clock signal, the second plurality ofdata-input ports would be strobed by the delayed-clock clock signal.Thus, the second plurality of data-input ports 415 would receive,sample, and store the second portion of data.

[0041] In some embodiments of the invention, the clock signal would bereceived from the bus via clock-receiving circuit 430. In otherembodiments of the invention (not shown), the clock signal would bereceived from another source.

5.5 Methods of Transferring Data

[0042]FIG. 5 presents a high-level block diagram of a system that isoperable to broadcast N, an even integer, data-bits onto a bus thatincludes a first plurality of electrical conductors 510 and a secondplurality of electrical conductors 520.

[0043]FIG. 6 presents one method of operating the system shown in FIG.5. First, as shown in Block 601, the data-transmitter 530 broadcasts afirst portion of data that includes N/2 data-bits onto the firstplurality of electrical conductors 510. In some embodiments of theinvention, the first portion of data may be the even data-bits. In otherembodiments of the invention, the first portion of data may be the odddata-bits.

[0044] Next, referring to Block 602, after a time period that is greaterthan 0 seconds and less than the time period required to transfer 2 bitsof data sequentially from the data-transmitter 530 to the data-receiver540 on any single electrical conductor on the bus, the data-transmitter530 broadcasts a second portion of data that includes N/2 bits of dataonto the second plurality of electrical conductors. In some embodimentsof the invention, the second portion of data may be the odd data-bits.In other embodiments of the invention, the second portion of data may bethe even data-bits.

[0045] If the above time period is equal to or greater than ¾ of the bittransition time of the data-bits on the bus, then the effectivecapacitive coupling between adjacent data-bits in the bus can besignificantly reduced. Such a method would be particularly useful if thebus transfers an even data-bit on a electrical conductor that isadjacent, for a length greater than 300 μm, to a electrical conductorthat transfers an odd data-bit.

5.6 Conclusion

[0046] The foregoing descriptions of embodiments of the presentinvention have been presented for purposes of illustration anddescription only. They are not intended to be exhaustive or to limit thepresent invention to the forms disclosed. Accordingly, manymodifications and variations will be apparent to practitioners skilledin the art. The data-transmitters, data-receivers and methods describedabove can be utilized in transferring data to and from electricalelements, such as registers in microprocessors, and digital signalprocessors. In addition, they can be utilized to transfer data betweencomputer systems connected by cables. Additionally, the above disclosureis not intended to limit the present invention. The scope of the presentinvention is defined by the appended claims.

It is claimed:
 1. A data-transmitter for transmitting data, thedata-transmitter comprising: a) a data-driving circuit, the data-drivingcircuit operable to output a first plurality of data values via a firstplurality of data-output ports and operable to output a second pluralityof data values via a second plurality of data-output ports; b) aplurality of data-delay circuits, each of the inputs of the plurality ofdata-delay circuits being coupled to one of the second plurality ofdata-output ports; and c) a plurality of electrical conductors, each ofthe plurality of electrical conductors being coupled to one of the firstplurality of data-output ports.
 2. The data transmitter of claim 1,wherein one of the plurality of electrical conductors is positionedbetween a first data-delay circuit of the plurality of data-delaycircuits and a second data-delay circuit of the plurality of data-delaycircuits.
 3. The data transmitter of claim 1, further comprising: d) aclock-driving circuit, the clock-driving circuit operable to output aclock via a clock-output port; and e) a clock-delay circuit, the inputof the clock-delay circuit being coupled to the clock-output port. 4.The data-transmitter of claim 1, wherein at least one of the pluralityof data-delay circuits includes two inverters.
 5. The data-transmitterof claim 1, wherein the data-transmitter is a register.
 6. Thedata-transmitter of claim 1, wherein the data-transmitter is operable tobroadcast a portion of a byte of data.
 7. The circuit of claim 1,wherein the first plurality of data-output ports is operable to transfera portion of a byte of data.
 8. The circuit of claim 1, wherein thefirst plurality of data-output ports is operable to output a firstportion of a byte of data and the second plurality of data-output portsis operable to output a second portion of the byte of data.
 9. Adata-transmitter for transmitting data, the data-transmitter comprising:a) a data-driving circuit, the data-driving circuit operable to output afirst plurality of data values via a first plurality of data-outputports and operable to output a second plurality of data values via asecond plurality of data-output ports; and b) a clock-delay circuit, theinput of the clock-delay circuit coupled to and operable to strobe thefirst plurality of data-output ports, the output of the clock-delaycircuit coupled to and operable to strobe the second plurality ofdata-output ports.
 10. The data transmitter of claim 9, furthercomprising: c) a clock-driving circuit, the clock-driving circuitoperable to output a clock via a clock-output port.
 11. Thedata-transmitter of claim 9, wherein the clock-delay circuit includestwo inverters.
 12. The data-transmitter of claim 9, wherein thedata-transmitter is a register.
 13. The data-transmitter of claim 9,wherein the data-transmitter is operable to broadcast a portion of abyte of data.
 14. The circuit of claim 9, wherein the first plurality ofdata-output ports is operable to transfer a portion of a byte of data.15. The circuit of claim 9, wherein the first plurality of data-outputports is operable to output a first portion of a byte of data and thesecond plurality of data-output ports is operable to output a secondportion of the byte of data.
 16. A data-receiver for receiving data, thedata-receiver comprising: a) a plurality of data-delay circuits; b) aplurality of electrical conductors; and c) a data-receiving circuit, thedata-receiving circuit including a first plurality of data-input portsand a second plurality of data-input ports, the first plurality ofdata-input ports being operable to receive, sample, and store a firstplurality of data values, the second plurality of data-input ports beingoperable to receive, sample, and store a second plurality of datavalues, each of the outputs of the plurality of data-delay circuitsbeing coupled to one of the first plurality of data-input ports of thedata-receiving circuit, and each of the plurality of electricalconductors being coupled to one of the second plurality of data-inputports of the data-receiving circuit.
 17. The data-receiver of claim 16,wherein one of the plurality of electrical conductors is positionedbetween a first data-delay circuit of the plurality of data-delaycircuits and a second data-delay circuit of the plurality of data-delaycircuits.
 18. The data-receiver of claim 16, further comprising: a) aclock-receiving circuit, the clock-receiving circuit operable to receivea clock signal; and b) a clock-delay circuit, the output of theclock-delay circuit being coupled to the clock-receiving circuit. 19.The data-receiver of claim 16, wherein at least one of the plurality ofdata-delay circuits includes two inverters.
 20. The data-receiver ofclaim 16, wherein the data-receiver is a register.
 21. The circuit ofclaim 16, wherein the first plurality of data-input ports is operable toreceive a portion of a byte of data.
 22. The circuit of claim 16,wherein the first plurality of data-input ports is operable to receive afirst portion of a byte of data and the second plurality of data-inputports is operable to receive a second portion of the byte of data.
 23. Adata-receiver for receiving data, the data-receiver comprising: a) aclock-delay circuit, the clock-delay circuit operable to delay a clocksignal and operable to output a delayed-clock signal; b) a firstplurality of data-ports, the first plurality of data-ports operable toreceive a first portion of data, the first plurality of data-portscoupled to and operable to be strobed by the clock signal; and c) asecond plurality of data-ports, the second plurality of data-portsoperable to receive a second portion of data, the second plurality ofdata-ports operable to be strobed by the delayed-clock signal.
 24. Thedata-receiver of claim 23, wherein the clock-delay circuit includes twoinverters.
 25. The data-receiver of claim 23, wherein the data-receiveris a register.
 26. The data-receiver of claim 23, wherein the firstplurality of data-input ports is operable to receive a portion of a byteof data.
 27. The data-receiver of claim 23, wherein the first pluralityof data-input ports is operable to receive a first portion of a byte ofdata and the second plurality of data-input ports is operable to receivea second portion of the byte of data.
 28. The data-receiver of claim 23,further including a clock-receiving circuit, the clock-receiving circuitoperable to receive the clock, the clock-receiving circuit coupled tothe clock-delay circuit.
 29. A method of broadcasting N, an eveninteger, bits of data onto a bus that includes a first plurality ofelectrical conductors and a second plurality of electrical conductors,the method comprising: a) broadcasting a first portion of data thatincludes N/2 bits of data onto the first plurality of electricalconductors; and b) after a time period that is greater than 0 secondsand less than the time period required to transfer 2 bits of datasequentially on one of the first plurality of electrical conductors,then broadcasting a second portion of data that includes N/2 bits ofdata onto the second plurality of electrical conductors.
 30. The methodof claim 29, wherein the act of broadcasting the first portion of dataincludes broadcasting a plurality of even data-bits.
 31. The method ofclaim 29, wherein the act of broadcasting the first portion of dataincludes broadcasting a plurality of odd data-bits.
 32. The method ofclaim 29, wherein the act of broadcasting the second portion of dataincludes broadcasting a plurality of even data-bits.
 33. The method ofclaim 29, wherein the act of broadcasting the second portion of dataincludes broadcasting a plurality of odd data-bits.
 34. The method ofclaim 29, wherein the act of broadcasting a first portion of dataincludes broadcasting the first portion from a register onto the bus.35. The method of claim 29, wherein the act of broadcasting a firstportion of data includes broadcasting the first portion from a registeronto a microprocessor bus.
 36. The method of claim 29, wherein the actof broadcasting the first portion of data includes broadcasting thefirst portion of data onto a bus that is operable to transfer an evendata-bit on a electrical conductor that is adjacent, for a lengthgreater than 300 μm, to a electrical conductor that is operable totransfer an odd data-bit.
 37. The method of claim 29, wherein the act ofbroadcasting the second portion of data after a time period includesbroadcasting the second portion of data after a time period that isgreater than ¾ of the transition time of data-bits on the bus.
 38. Themethod of claim 29, wherein the act of broadcasting the second portionof data after a time period includes broadcasting the second portion ofdata after a time period that is greater than 75 ps.